This invention relates generally to an integrated circuit interconnection structure including multiple metal layers and more particularly to a multiple layer interconnection structure including a high temperature low ohmic refractory metal contact assembly and interconnect layers cooperating with the structure and contact assembly.
It is well known that a multi-layer integrated circuit interconnection structure is desirable to improve circuit performance as well as to increase circuit density. Prior art structures include etched contact holes formed in an oxide-coated wafer surface, a layer of aluminum formed on the oxide surface and in the contact holes to form contacts with selected regions of the wafer. The aluminum layer is patterned to interconnect specific portions of the integrated circuit. This contact and interconnection structure has not been especially satisfactory for many applications because the highly reactive aluminum pits the silicon oxide during high temperature processing reducing the structure's breakdown voltage. Subsequent processing steps such as passivation and multi-layer interconnection increases the reaction between the aluminum and the silicon oxide. Elevated temperatures required for some processing steps, of the order of 900.degree. C., further promote aluminum and oxide reaction. The aluminum may recrystallize in formations which crack the insulating layer separating multiple metal layers. Thus, the use of aluminum contacts and interconnections severely restricts subsequent processing steps at elevated temperatures.
Prior art complementary MOS and metal layer structures include the silicon gate structure having the surface of the semiconductor body lined with a silicon layer forming a gate structure. The first metallization layer is formed of silicon in a process step prior to the step of forming source and drain regions extending into the semiconductor body. The surface lined silicon gate structure limits the flexibility and density of complementary MOS circuits. Because the first layer of metal cannot cross the channel stops, the surface silicon gate structure can prevent the use of isolating channel stops surrounding the complementary MOS transistors. If channel stops ae used, silicon gate reserves the first metallization layer solely for contacting the transistor gates, again because the first layer of metal cannot cross in the same plane the isolating channel stops. The silicon gate structure, when combined with channel stops, severely restricts the possible metallization interconnections in complementary MOS circuits.